The present invention relates to delay lock loops (DLLs) for digital electronics. More specifically, the present invention relates to DLLs capable of locking clock signals over a wide frequency range.
Synchronous digital systems, including board level systems and chip level systems, rely on one or more clock signals to synchronize elements across the system. Typically, one or more clock signals are distributed across the system on one or more clock lines. However, due to various problems such as clock buffer delays, high capacitance of heavily loaded clock lines, and propagation delays, the rising edges of a clock signal in different parts of the system may not be synchronized. The time difference between a rising (or falling) edge in one part of the system with the corresponding rising (or falling) edge in another part of the system is referred to as xe2x80x9cclock skewxe2x80x9d.
Clock skew can cause digital systems to malfunction. For example, it is common for circuits in digital systems to have a first flip-flop output driving a second flip-flop input. With a synchronized clock on the clock input of both flip-flops, the data in the first flip-flop is successfully clocked into the second flip-flop. However, if the active edge on the second flip flop is delayed by clock skew, the second flip-flop might not capture the data from the first flip-flop before the first flip-flop changes state.
Delay lock loops are used in digital systems to minimize clock skew. Delay lock loops typically use delay elements to synchronize the active edges of a reference clock signal in one part of the system with a feedback clock signal from a second part of the system. FIG. 1 shows a block diagram of a conventional delay lock loop 100 coupled to logic circuits 190. Delay lock loop 100, which comprises a delay line 110 and a phase detector 120, receives a reference clock signal REF_CLK and drives an output clock signal O_CLK.
Delay line 110 delays reference clock signal REF_CLK by a variable propagation delay D before providing output clock signal O_CLK. Thus, each clock edge of output clock signal O_CLK lags a corresponding clock edge of reference clock signal REF_CLK by propagation delay D (see FIG. 2A). Phase detector 120 controls delay line 110, as described below. Delay line 110 is capable of producing a minimum propagation delay D_MIN and a maximum propagation delay D_MAX.
Before output clock signal O_CLK reaches logic circuits 190, output clock signal O_CLK is skewed by clock skew 180. Clock skew 180 can be caused by delays in various clock buffers (not shown) or propagation delays on the clock signal line carrying output clock signal O_CLK (e.g., due to heavy, loading on the clock signal line). To distinguish output clock signal O_CLK from the skewed version of output clock signal O_CLK, the skewed version is referred to as skewed clock signal S_CLK. Skewed clock signal S_CLK drives the clock input terminals (not shown) of the clocked circuits within logic circuits 190. Skewed clock signal S_CLK is also routed back to delay lock loop 100 on a feedback path 170. Typically, feedback path 170 is dedicated specifically to routing skewed clock signal S_CLK to delay lock loop 110. Therefore, any propagation delay on feedback path 170 is minimal and causes only negligible skewing.
FIG. 2A provides a timing diagram of reference clock signal REF_CLK, output clock signal O_CLK, and skewed clock signal S_CLK. All three clock signals have the same frequency F (not shown) and period P, and all are active-high (i.e., the rising edge is the active edge). Since output clock signal O_CLK is delayed by propagation delay D, a clock edge 220 of output clock signal O_CLK lags corresponding clock edge 210 of reference clock signal REF_CLK by propagation delay D. Similarly, a clock edge 230 of skewed clock signal S_CLK lags corresponding clock edge 220 of output clock signal O_CLK by a propagation delay SKEW, which is the propagation delay caused by clock skew 180 (FIG. 1). Therefore, clock edge 230 of skewed clock signal S_CLK lags clock edge 210 of reference clock signal REF_CLK by a propagation delay DSKEW, which is equal to propagation delay D plus propagation delay SKEW.
Delay lock loop 100 controls propagation delay D by controlling delay line 110. However, delay line 110 cannot create negative delay; therefore, clock edge 230 cannot be synchronized to clock edge 210. Fortunately, clock signals are periodic signals. Therefore, delay lock loop 100 can synchronize reference clock signal REF_CLK and skewed clock signal S_CLK by further delaying output clock signal O_CLK such that clock edge 240 of skewed clock signal S_CLK is synchronized with clock edge 210 of reference clock signal REF_CLK. As shown in FIG. 2B, propagation delay D is adjusted so that propagation delay DSKEW is equal to period P. Specifically, delay line 110 is tuned so that propagation delay D is increased until propagation delay D equals period P minus propagation delay SKEW. Although propagation delay DSKEW could be increased to any multiple of period P to achieve synchronization, most delay lock loops do not include a delay line capable of creating such a large propagation delay.
Phase detector 120 (FIG. 1) controls delay line 110 to regulate propagation delay D. The actual control mechanism for delay lock loop 100 can differ. For example, in one version of delay lock loop 100, delay line 110 starts with a propagation delay D equal to minimum propagation delay D_MIN, after power-on or reset. Phase detector 110 then increases propagation delay D until reference clock signal REF_CLK is synchronized with skewed clock signal S_CLK. In another system, delay lock loop 100 starts with a propagation delay D equal to the average of minimum propagation delay D_MIN and maximum propagation delay D_MAX, after power-on or reset. Phase detector 120 then determines whether to increase or decrease (or neither) propagation delay D to synchronize reference clock signal REF_CLK with skewed clock signal S_CLK. For example, phase detector 120 would increase propagation delay D for the clock signals depicted in FIG. 2A. However, phase detector 120 would decrease propagation delay D for the clock signals depicted in FIG. 2C.
In FIG. 2C, skewed clock signal S_CLK is said to xe2x80x9clagxe2x80x9d reference clock signal REF_CLK, because the time between a rising edge of reference clock signal REF_CLK and the next rising edge of skewed clock signal S_CLK is less than the time between a rising edge of skewed clock signal S_CLK and the next rising edge of reference clock signal REF_CLK. However, in FIG. 2A, reference clock signal REF_CLK is said to xe2x80x9clagxe2x80x9d skewed clock signal S_CLK, because the time between a rising edge of skewed clock signal S_CLK and the next rising edge of reference clock signal REF_CLK is less than the time between a rising edge of reference clock signal REF_CLK and the next rising clock edge of skewed clock signal S_CLK. Alternatively, in FIG. 2A skewed clock signal S_CLK could be said to xe2x80x9cleadxe2x80x9d reference clock signal REF_CLK.
After synchronizing reference clock signal REF_CLK and skewed clock signal S_CLK, delay lock loop 100 monitors reference clock signal REF_CLK and skewed clock signal S_CLK and adjusts propagation delay D to maintain synchronization. For example, if propagation delay SKEW increases, perhaps caused by an increase in temperature, delay lock loop 100 must decrease propagation delay D to compensate. Conversely, if propagation delay SKEW decreases, perhaps caused by a decrease in temperature, delay lock loop 100 must increase propagation delay D to compensate. The time in which delay lock loop 100 is attempting to first synchronize reference clock signal REF_CLK and skewed clock signal S_CLK, is referred to as lock acquisition. The time in which delay lock loop 100 is attempting to maintain synchronization is referred to as lock maintenance. The value of propagation delay D at the end of lock acquisition, i.e. when synchronization is initially established, is referred to as initial propagation delay ID.
However, as explained above, delay line 110 can only provide a propagation delay between a minimum propagation delay D_MIN and a maximum propagation delay D_MAX. During lock maintenance, delay lock loop 100 may lose synchronization if a propagation delay D smaller than minimum propagation delay D_MIN is required to maintain synchronization. Similarly, synchronization may be lost if a propagation delay D greater than maximum propagation delay D_MAX is required to maintain synchronization.
For example, if lock acquisition occurs while the system using delay lock loop 100 is at a very high temperature, delay lock loop 100 is likely to achieve synchronization with a very small initial propagation delay ID, since propagation delay SKEW is likely to be large with respect to period P. As the system""s temperature increases further, propagation delay SKEW is likely to increase to a point where propagation delay SKEW plus minimum propagation delay D_MIN is greater than period P. In this situation, delay lock loop 100 must undergo lock acquisition again, which may introduce glitches and noise into output clock signal O_CLK, in turn causing glitches and noise in skewed clock signal S_CLK. For critical systems, such glitches are intolerable. Further, for systems designed for operation at multiple clock frequencies, low frequency operation is likely to compound the problems since clock period P is very long. Long clock periods may cause propagation delay D to vary over a wider time interval. Thus, there is a need for a delay lock loop which can maintain synchronization over a wide range of clock frequencies and environmental extremes.
In addition, conventional delay lock loop circuits provide for precise synchronization of the reference clock signal REF_CLK and the skew clock signal S_CLK. It would be desirable to have a delay lock loop circuit which is capable of providing a skew clock signal S_CLK which is precisely shifted by a relatively small amount with respect to the reference clock signal REF_CLK. It would further be desirable if such delay lock loop circuit were capable of providing both a leading and lagging relationship. Such a delay lock loop circuit would enable the precise control of clock phase in logic circuits. Such control allows, for example, more accurate timing budget allocation, which in turn, allows synchronous digital systems to run at faster speeds.
Delay lock loop circuit 100 provides an S_CLK signal having a single frequency in response to the REF_CLK signal. For example, the S_CLK signal may have a frequency of 100 MHz. The Federal Communications Commission (FCC) has provided limits on the electromagnetic energy that a chip may emit within a specified frequency bandwidth, which depends on the characteristics of the system being tested. One such measurement method employs a 1 MHz bandwidth window. Because all of the energy emitted by the S_CLK signal exists at a single frequency, all of the energy will also exist within such a window. Therefore, for systems that violate FCC limits, special techniques must be employed to reach compliance. Conventional compliance techniques include the use of stand-alone (i.e., off-chip) spread spectrum clock oscillators and metal shielding around the radiating components.
It would therefore be desirable to have a clock system that overcomes the electromagnetic emission limitations of delay lock loop 100.
The present invention provides a delay lock loop that synchronizes the reference clock signal with the skewed clock signal using a delay line having an initial propagation delay within a lock window. The lock window is a period of time between the minimum delay of the propagation delay and the maximum propagation delay. The extent of the lock window is chosen to ensure that changes in environmental conditions or clock frequencies, when compensated for by changing the propagation delay of the delay line, do not cause a loss of synchronization. A delay lock loop in accordance with one embodiment of the present invention incorporates a clock phase shifter in addition to the delay line to synchronize the reference clock. The increased flexibility provided by the clock phase shifter increases the range of frequencies at which the delay lock loop will operate.
The delay line receives the reference clock signal from a reference input terminal of the delay lock loop. The output of the delay line (i.e., the delayed clock signal) is provided to the clock phase shifter, which can generate one or more phase-shifted clock signals. An output generator receives the delayed clock signal and the one or more phase-shifted clock signals. The output generator provides one of the clock signals as the output clock signal on an output terminal. A phase detector compares the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop, to determine whether to increase or decrease the propagation delay of the delay line to synchronize the reference clock signal and the skewed clock signal.
One embodiment of the clock phase shifter generates Nxe2x88x921 phase-shifted clock signals. Each of the phase-shifted clock signals is phase-shifted from the other Nxe2x88x922 clock signals and the delayed clock signal by 360/N degrees. For example, if the clock phase shifter generated 3 phase-shifted clock signals (i.e., N is equal to four), the phase-shifted clock signals would be phase-shifted from the delayed clock signal by 90 degrees, 180 degrees, and 270 degrees. The clock phase shifter can be implemented using N delay lines and a phase detector.
The delay lock loop can include a controller to control the delay line and the output generator. In one embodiment of the invention, the controller causes the output generator to drive the delayed clock signal as the output clock. The controller synchronizes the reference clock signal with the skewed clock signal by adjusting the propagation delay of the delay line to an initial delay. If the initial delay is not within the lock window, the controller causes the output generator to drive a first phase-shifted clock signal as the output signal. The controller and phase detector then synchronize the reference clock signal with the skewed clock signal by adjusting the propagation delay of the delay line to a second initial delay. If the second initial delay is not within the lock window, the controller causes the output generator to use a second phase-shifted clock signal as the output clock. The controller continues in this manner until an initial delay within the lock window is found.
In another embodiment of the invention, the clock phase shifter is coupled to receive the reference clock signal. The clock phase shifter generates phase-shifted clock signals that are phase-shifted from the reference clock signals. The reference clock signal or one of the phase-shifted clock signals from the clock shifter is selected to be the input signal of the delay line. The delay line is controlled by the controller and the phase detector to delay the input clock signal and synchronize the skewed clock signal with the reference clock signal.
After the delay lock loop synchronizes the reference clock signal with the skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. In accordance with one embodiment, the tap settings and the finer trim settings of a delay line in the clock phase shifter are transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a fraction of the period of the reference clock signal. In one embodiment, the period of the reference clock signal is determined from the tap/trim settings of a delay line in the clock phase shifter. The delay line can have, for example, 512 tap/trim units. The phase control signal is determined by multiplying the equivalent tap/trim units used by a delay line in the clock phase shifter by a fraction. The fraction can be determined by the contents of configuration memory bits stored in an FPGA, or by a user-defined signal.
The digital phase shifter can be controlled to operate in one of two fixed modes or in one of two variable modes. In the first fixed mode, the digital phase shifter introduces delay to the skew clock signal. For example, the digital phase shifter can introduce a delay in the range of 0 to 511 tap/trim units to the skew clock signal in the first fixed mode. In the second fixed mode, the digital phase shifter introduces delay to the reference clock signal. For example, the digital phase shifter can introduce a delay in the range of 0 to 511 tap/trim units to the reference clock signal in the second fixed mode. In the first variable mode, the digital phase shifter can introduce a delay equal to 255 to xe2x88x92255 tap/trim units to the reference clock signal. In the second variable mode, the digital phase shifter can introduce a delay equal to 255 to xe2x88x92255 tap/trim units to the skew clock signal.
In accordance with another embodiment, the digital phase shifter is capable of operating in a low frequency mode or a high frequency mode. The digital phase shifter is controlled to adjust the tap/trim setting provided by the delay line of the clock phase shifter to compensate for different overhead delays experienced by the clock phase shifter in the low frequency mode and the high frequency mode.
In yet another embodiment of the present invention, the frequency of the skew clock signal can be dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions in many cases. That is, delay can be introduced such that the skew clock signal exhibits slightly different frequencies in successive periods. For example, the frequency of a 100 MHz clock signal can be adjusted to have frequencies of approximately 98, 98.5, 99, 99.5, 100, 100.5, 101, 101.5, and 102 MHz during different periods. This configuration is referred to as a xe2x80x9cspread-8xe2x80x9d configuration, because eight frequencies are generated in addition to the base frequency of 100 MHz. For a 1 MHz window measurement method, because the frequencies are spread in 0.5 MHz increments, only three of the nine frequencies are included in the window. As a result, ⅔ of the energy of the clock signal is not included when determining whether the clock signal meets the FCC electromagnetic emission requirements. By spreading the frequencies above and below the base frequency in a regular manner, the average frequency of the clock signal becomes equal to the base frequency. Other configurations, including, but not limited to, spread-2, spread-4 and spread-6 configurations, can be implemented in accordance with the present invention.
In a preferred embodiment, the clock frequencies are generated by a digital spread spectrum (DSS) circuit, which operates with the digital phase shifter to insert small delays in the skew clock signal. Because the digital phase shifter delay must be able to adjust both up and down relative to its starting point, the variable mode of the digital phase shifter is typically used in conjunction with the DSS circuit. In accordance with one embodiment, the DSS circuit provides particular patterns of digital tap/trim adjustments to optimize the operation of the digital phase shifter.
In another embodiment, the DSS circuit and/or pattern of digital tap/trim adjustments necessary to successfully implement spread spectrum generation can be used with a conventional delay line, independent of the digital phase shifter.